1. Field of the Invention
The present invention relates to a semiconductor memory device and a system on which the semiconductor memory device is mounted. More particularly, the invention relates to a semiconductor memory device for outputting data synchronously with a clock signal and a system on which the semiconductor memory device is mounted.
2. Description of the Background Art
In recent years, in order to transfer/receive data at high speed, a double data rate synchronous dynamic random access memory (DDR SDRAM) capable of outputting data synchronously with both rising and falling edges of a clock signal is used.
On a system using this memory, in many cases, a plurality of DDR SDRAMs and a controller for transmitting/receiving data to/from the DDR SDRAMs are mounted.
In such a memory system, external clock signals of the same phase are input to the controller and the DDR SDRAMs. The DDR SDRAM is designed so that a data output signal DQ is switched at the phase of the rising edge and that of the falling edge of an external clock signal supplied.
FIG. 14 is a block diagram showing the configuration of a conventional DDR SDRAM 501.
Referring to FIG. 14, DDR SDRAM 501 includes an address buffer 504 for receiving external address signals A0 to A11 and bank address signals BA0 and BA1 and generating internal address signals INTA0 to INTA11; a clock signal buffer 502 for receiving external clock signals CLK and /CLK and a clock enable signal CKE and generating an internal clock signal ICLK; a control signal buffer 506 for receiving a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, and input/output DQ mask signals UDM and LDM synchronously with internal clock signal ICLK; a control circuit 508 for receiving internal clock signal ICLK, internal address signals INTA0 to INTA11 and an output of control signal buffer 506 and controlling the whole chip; and a mode register 510 for holding an operation mode of the SDRAM according to an output of the control signal buffer in response to an instruction of control circuit 508.
DDR SDRAM 501 further includes: a DQ buffer 514 for transmitting/receiving a data signal to/from an external data bus; and memory arrays 512a to 512d for holding data input from the outside. Memory arrays 512a to 512d are four banks which can operate independent of each other.
DDR SDRAM 501 further includes: a DLL (Delay Locked Loop) circuit 516 for receiving internal clock signal ICLK as a clock signal BUFFCLK from clock signal buffer 502 and outputting a clock signal CLKP to DQ buffer 514; and a QFC and QS buffer 518 for outputting control signals /QFC, UDQS, and LDQS in accordance with control timings of DQ buffer 514.
Control signal /QFC can be used as a control signal for isolating the external bus from other devices when a read or write access is made to DDR SDRAM. Control signals UDQS and LDQS are strobe signals used by a controller to capture a data signal outputted to the external data bus.
FIG. 15 is a diagram for explaining the configuration of mode register 510 and control circuit 508 in FIG. 14.
Referring to FIG. 15, the control circuit 508 includes a command decoder 622 for receiving and decoding an output of control signal buffer 506 to detect a command and, when a mode register set command is detected, activating a control signal /MSET to the L level; an inverter 624 for receiving and inverting control signal /MSET and outputting a control signal MSET; and clocked inverters 650 to 652 which are made active in association with activation of the control signal MSET, and receive and invert internal address signals INTA0 to INTA2, respectively, from address buffer 504.
For simplicity of explanation, the configuration of control circuit 508 only with respect to the portion of writing data to mode register 510 is shown.
Mode register 510 includes latch circuits 630 to 632 for receiving outputs of clocked inverters 650 to 652, respectively, and inverters 640 to 642 for receiving and inverting outputs of latch circuits 630 to 632 and outputting signals K0 to K2, respectively.
Latch circuit 630 includes an inverter 662 for receiving and inverting an output of clocked inverter 650, and an inverter 660 for receiving and inverting an output of inverter 662 and feeding back the resultant to the input of inverter 662. Since the configuration of each of latch circuits 631 and 632 is similar to that of latch circuit 630, its description will not be repeated.
FIG. 16 is a circuit diagram showing the configuration of DLL circuit 516 in FIG. 14.
Referring to FIG. 16, DLL circuit 516 includes: a delay line 32 for delaying clock signal BUFFCLK and outputting a clock signal CLKP; a replica buffer 34 for receiving clock signal CLKP, compensating delay time of DQ buffer 514 in FIG. 14 as an output buffer, and outputting a clock signal FBCLK; and a phase comparator 38 for comparing the phase of clock signal BUFFCLK and that of clock signal FBCLK and outputting control signals a[0] to a[2].
Delay line 32 receives clock signal BUFFCLK by its node N1. Delay line 32 includes: an N-channel MOS transistor 44 connected between nodes N1 and N2 and for receiving control signal a[0] by its gate; a delay circuit 56 whose input is connected to node N2 and whose output is connected to a node N3; and a P-channel MOS transistor 46 connected between nodes N1 and N3 and for receiving control signal a[0] by its gate.
Delay line 32 further includes: an N-channel MOS transistor 48 connected between nodes N3 and N4 and for receiving control signal a[1] by its gate; a delay circuit 58 whose input is connected to node N4 and whose output is connected to a node N5; and a P-channel MOS transistor 50 connected between nodes N3 and N5 and for receiving control signal a[1] by its gate.
Delay line 32 further includes: an N-channel MOS transistor 52 connected between nodes N5 and N6 and for receiving control signal a[2] by its gate; a delay circuit 60 whose input is connected to node N6 and whose output is connected to a node N7; and a P-channel MOS transistor 54 connected between nodes N5 and N7 and for receiving control signal a[2] by its gate.
Delay circuit 56 includes two inverters connected in series. Delay circuit 58 includes four inverters connected in series. Delay circuit 60 includes eight inverters connected in series.
Replica buffer 34 includes inverters connected in series having delay time corresponding to delay time of DQ buffer 514.
FIGS. 17 and 18 are operational waveform charts for explaining the operation of DLL circuit 516 shown in FIG. 16.
First, by referring to FIGS. 16 and 17, clock signal BUFFCLK goes high at time t1 and, in response to this, clock signal CLKP goes high at time t2 after the delay time of delay line 32.
At time t3 after the delay time of replica buffer 34 for compensating a delay in an output buffer since time t2, clock signal FBCLK goes high.
Phase comparator 38 compares the rising edge of clock signal FBCLK at time t3 and that of clock signal BUFFCLK at time t4, and determines that the phase of clock signal FBCLK is advanced as compared with that of clock signal BUFFCLK.
Phase comparator 38 changes a control signal A[2:0] to increase delay time of delay line 32.
Referring now to FIGS. 16 and 18, after the delay time of delay line 32 is increased, delay time during a period from rising time t1 of clock signal BUFFCLK to rising time t2 of clock signal CLKP increases. At time t3, the phase at the rising edge of clock signal BUFFCLK and that at the rising edge of clock signal FBCLK coincides with each other.
As described above, the conventional DDR SDRAM is designed so that the data DQ is switched in the terminal portion with the same phase as that of external clock signal CLK supplied to the chip.
In the system using the DDR SDRAM, usually, a plurality of DDR SDRAMs are mounted on a board and reading/writing operations are performed on the DDR SDRAMs in a lump.
FIG. 19 is a diagram showing a schematic configuration of a system using the conventional DDR SDRAM.
Referring to FIG. 19, the conventional memory system includes: a clock generator 534 for supplying clock signal CLK to the system; DDR SDRAMs 501a and 501b for outputting data DQA and DQB to data buses connected to the outside; and a controller 532 for receiving clock signal CLK as an operation clock and capturing data DQA and DQB.
An example of such a memory system is a mother board on which a microprocessor using a DDR SDRAM as an external storage is mounted.
FIG. 20 is an operational waveform chart for explaining data transmission/reception of the memory system shown in FIG. 19.
Referring to FIGS. 19 and 20, each of DDR SDRAMs is controlled so that data signal DQ and strobe signal DQS change synchronously with the rising and falling edges of the clock signal CLK.
In each of DDR SDRAMs 501a and 501b, data signal DQ and strobe signal DQS are outputted from the terminal portion simultaneously with the rising edge of clock signal CLK at time t1.
However, data signal DQA outputted at time t1 from DDR SDRAM 501a arrives at controller 532 at time t2.
On the other hand, data signal DQB outputted at time t1 from DDR SDRAM 501b arrives at controller 532 at time t3. When data is captured synchronously with clock signal CLK supplied to the controller, a margin of data is decreased.
Consequently, each DDR SDRAM outputs data strobe signal DQS having the same phase as that of external clock signal on the chip at the time of data output. Controller 532 captures data signal DQA in response to strobe signal DQSA outputted from DDR SDRAM 501a, and captures data signal DQB in response to strobe signal DQSB outputted from SDRAM 501b. 
Even when flight time of DDR SDRAMs is different from each other, by capturing data in response to strobe signal, controller 532 can receive data at high speed.
There is, however, a drawback such that since strobe signal DQS and data signal DQ are transmitted to controller 532 with phases various according to the DDR SDRAMs, signals of various phases have to be processed in controller 532, so that the burden on the controller 532 is heavy. It causes a problem such that the configuration of controller 532 is complicated.
Although the system on which DDR SDRAMs are mounted has been described above as an example, it can be said that all of systems in which output data is input from memories to controller with phases varying according to the memories have similar drawbacks.
An object of the invention is to provide a semiconductor memory device capable of adjusting arriving time of data in a system using a plurality of semiconductor memory devices and further to provide a memory system and a memory module each capable of transferring data at high speed with a simple configuration.
The invention relates to, in short, a semiconductor memory device for outputting data synchronously with an external clock signal supplied from the outside, which has an internal clock generating circuit, a memory array, and an output buffer circuit.
The internal clock generating circuit outputs a first internal clock signal synchronously with the external clock signal. The internal clock generating circuit adjusts a phase difference between the external clock signal and the first internal clock signal in accordance with a set value supplied from the outside. The memory array includes a plurality of memory cells for holding the data. The output buffer circuit outputs data read from the memory array synchronously with the first internal clock signal.
According to another aspect of the invention, a memory system including a clock generating circuit, a controller, and a plurality of semiconductor memory devices is provided.
The clock generating circuit generates a system clock signal. The controller receives a data signal synchronously with the system clock signal. The plurality of semiconductor memory devices output the data signal to the controller synchronously with the system clock signal.
Each of the semiconductor memory devices includes an internal clock generating circuit for outputting a first internal clock signal synchronously with the system clock signal. The internal clock generating circuit adjusts a phase difference between the system clock signal and the first internal clock signal in accordance with a set value supplied.
Each of the plurality of semiconductor memory devices further includes a memory array including a plurality of memory cells for holding the data and an output buffer circuit for outputting, as the data signal, the data read from the memory array synchronously with the first internal clock signal.
According to further another aspect of the invention, a memory module having a plurality of semiconductor memory devices for outputting a data signal synchronously with a system clock signal is provided.
Each of the plurality of semiconductor memory devices includes an internal clock generating circuit for outputting a first internal clock signal synchronously with the system clock signal. The internal clock generating circuit adjusts a phase difference between the system clock signal and the first internal clock signal in accordance with a set value supplied.
Each of the plurality of semiconductor memory devices further includes: a memory array including a plurality of memory cells for holding data; and an output buffer circuit for outputting, as the data signal, the data read from the memory array synchronously with the first internal clock signal.
Therefore, a main advantage of the invention is that, since the phase of the data output signal which is output synchronously with the clock signal can be changed according to the set value supplied, by adjusting the phases of data outputs in the memory system, burden on the controller can be lessened.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.